SGDK
A free and open development kit for the Sega Mega Drive
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16c550

Simple 16C550 UART chip driver. More...

Collaboration diagram for 16c550:

Topics

 UartRegs
 16C550 UART registers
 UartOuts
 Output pins controlled by the MCR UART register.
 UartIns
 Input pins readed in the MSR UART register.

Classes

struct  UartShadow
 Structure with the shadow registers. More...

Macros

#define UART_BASE   0xA130C1
 16C550 UART base address
#define UART_CLK   24000000LU
 Clock applied to 16C550 chip. Currently using 24 MHz crystal.
#define UART_BR   1500000LU
#define UART_TX_FIFO_LEN   16
 Length of the TX FIFO in bytes.
#define DivWithRounding(dividend, divisor)
 Division with one bit rounding, useful for divisor calculations.
#define UART_DLM_VAL   (DivWithRounding(UART_CLK, 16 * UART_BR)>>8)
 Value to load on the UART divisor, high byte.
#define UART_DLL_VAL   (DivWithRounding(UART_CLK, 16 * UART_BR) & 0xFF)
 Value to load on the UART divisor, low byte.
#define uart_tx_ready()
 Checks if UART transmit register/FIFO is ready. In FIFO mode, up to 16 characters can be loaded each time transmitter is ready.
#define uart_rx_ready()
 Checks if UART receive register/FIFO has data available.
#define uart_putc(c)
 Sends a character. Please make sure there is room in the transmit register/FIFO by calling uart_rx_ready() before using this function.
#define uart_getc()
 Returns a received character. Please make sure data is available by calling uart_rx_ready() before using this function.
#define uart_set(reg, val)
 Sets a value in IER, FCR, LCR or MCR register.
#define uart_get(reg)
 Gets value of IER, FCR, LCR or MCR register.
#define uart_set_bits(reg, val)
 Sets bits in IER, FCR, LCR or MCR register.
#define uart_clr_bits(reg, val)
 Clears bits in IER, FCR, LCR or MCR register.
#define uart_reset_fifos()
 Reset TX and RX FIFOs.
#define uart_test(reg, val)
 Test Connection with registers.

Functions

void uart_init (void)
 Initializes the driver. The baud rate is set to UART_BR, and the UART FIFOs are enabled. This function must be called before using any other API call.

Variables

UartShadow sh
 Uart shadow registers. Do NOT access directly!

Detailed Description

Simple 16C550 UART chip driver.

Author
Jesus Alonso (doragasu)
Date
2016

Macro Definition Documentation

◆ DivWithRounding

#define DivWithRounding ( dividend,
divisor )
Value:
((((dividend)*2/(divisor))+1)/2)

Division with one bit rounding, useful for divisor calculations.

◆ UART_BR

#define UART_BR   1500000LU

Desired baud rate. Maximum achievable baudrate with 24 MHz crystal is 24000000/16 = 1.5 Mbps

◆ uart_clr_bits

#define uart_clr_bits ( reg,
val )
Value:
do{sh.reg &= ~(val); \
UART_##reg = sh.reg;}while(0)
UartShadow sh
Uart shadow registers. Do NOT access directly!

Clears bits in IER, FCR, LCR or MCR register.

Parameters
[in]regRegister to modify (IER, FCR, LCR or MCR).
[in]valBits set in val, will be cleared in reg register.

◆ uart_get

#define uart_get ( reg)
Value:
(sh.reg)

Gets value of IER, FCR, LCR or MCR register.

Parameters
[in]regRegister to read (IER, FCR, LCR or MCR).
Returns
The value of the requested register.

◆ uart_getc

#define uart_getc ( )
Value:
#define UART_RHR
Receiver holding register. Read only.
Definition 16c550.h:48

Returns a received character. Please make sure data is available by calling uart_rx_ready() before using this function.

Returns
Received character.

◆ uart_putc

#define uart_putc ( c)
Value:
do{UART_RHR = (c);}while(0);

Sends a character. Please make sure there is room in the transmit register/FIFO by calling uart_rx_ready() before using this function.

Returns
Received character.

◆ uart_reset_fifos

#define uart_reset_fifos ( )
Value:
uart_set_bits(FCR, 0x07)
#define uart_set_bits(reg, val)
Sets bits in IER, FCR, LCR or MCR register.
Definition 16c550.h:160

Reset TX and RX FIFOs.

◆ uart_rx_ready

#define uart_rx_ready ( )
Value:
(UART_LSR & 0x01)
#define UART_LSR
Line status register. Read only.
Definition 16c550.h:62

Checks if UART receive register/FIFO has data available.

Returns
TRUE if at least 1 byte is available, FALSE otherwise.

◆ uart_set

#define uart_set ( reg,
val )
Value:
do{sh.reg = (val);UART_##reg = (val);}while(0)

Sets a value in IER, FCR, LCR or MCR register.

Parameters
[in]regRegister to modify (IER, FCR, LCR or MCR).
[in]valValue to set in IER, FCR, LCR or MCR register.

◆ uart_set_bits

#define uart_set_bits ( reg,
val )
Value:
do{sh.reg |= (val); \
UART_##reg = sh.reg;}while(0)

Sets bits in IER, FCR, LCR or MCR register.

Parameters
[in]regRegister to modify (IER, FCR, LCR or MCR).
[in]valBits set in val, will be set in reg register.

◆ uart_test

#define uart_test ( reg,
val )
Value:
reg = val; \
if (reg != val) return MW_ERR
@ MW_ERR
General error.
Definition megawifi.h:76

Test Connection with registers.

Parameters
[in]regRegister to modify
[in]valBits set in val, will be readed from reg register.

◆ uart_tx_ready

#define uart_tx_ready ( )
Value:
(UART_LSR & 0x20)

Checks if UART transmit register/FIFO is ready. In FIFO mode, up to 16 characters can be loaded each time transmitter is ready.

Returns
TRUE if transmitter is ready, FALSE otherwise.